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Ordering number : EN*4907
CMOS LSI
LC75710NE, 75711NE, 75712E
Dot Matrix VFD Display Controller/Driver
Preliminary Overview
The LC75710NE series products are dot matrix VFD controller/driver LSIs that display characters, numbers, and symbols. These LSIs generate dot matrix VFD drive signals based on serial data sent from a microprocessor, and allow display systems to be implemented easily using the built-in character generator ROM and RAM. The LC75710NE series products are fabricated in a CMOS process and can contribute to achieving low-power operation in user applications.
Differences between the LC75710NE, LC75711NE, and LC75712E
* The data in the built-in character generator ROM (CGROM) differs between these products. All other functions are identical.
Package Dimensions
unit: mm 3159-QFP64E
[LC75710NE, 75711NE, 75712E]
Features
* 5 x 7 dot matrix VFD display controller/driver (Driver outputs can be connected directly to VFD devices: pull-down resistors are not required.) * Display technique: Dynamic lighting technique * Display digits: 1 to 16 digits (programmable) * Display control data CGROM: 5 x 7 dots, 160 characters CGRAM: 5 x 7 dots, 8 characters ADRAM: 16 x 8 bits DCRAM: 64 x 8 bits * Instruction functions Display on/off control Display shift Display blink Intensity adjustment (dimmer) * Serial data input (DI, CL, and CE pins) * Built-in reset circuit * 64-pin flat package
SANYO: QIP64E
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
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31595TH (OT) No. 4907-1/21
LC75710NE, 75711NE, 75712E Pin Assignment and Sample Application Circuit
No. 4907-2/21
LC75710NE, 75711NE, 75712E
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VFL max VIN1 VIN2 IOUT1 Output current IOUT2 IOUT3 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD VFL OSCI DI, CL, CE, RES AM1 to AM35 AA1 to AA3 AA4 to AA8, G1 to G16 Ta 85C, with up to 70% of the AM1 to AM35 outputs driven Conditions Ratings -0.3 to +6.5 VDD - 55 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +6.5 1 10 20 400 -40 to +85 -50 to +125 mW C C mA Unit V
Input voltage
V
Allowable Operating Ranges at Ta = -40 to +85C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter Supply voltage Symbol VDD VFL VIH1 Input high level voltage VIH2 VIH3 Input low level voltage Guaranteed oscillator range Recommended external resistor Recommended external capacitor Minimum reset pulse width Low level clock pulse width High level clock pulse width Data setup time Data hold time CE wait time CE setup time CE hold time VIL1 VIL2 fOSC ROSC COSC tWRES toL toH tDS tDH tCP tCS tCH VDD VFL DI, CL, CE RES OSCI DI, CL, CE RES, OSCI OSCI, OSCO OSCI, OSCO OSCI, OSCO RES CL CL DI, CL DI, CL CE, CL CE, CL CE, CL 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Conditions min 4.5 VDD - 50 0.8 VDD 0.7 VDD 0.7 VDD 0 0 1.0 2.7 10 30 typ 5.0 max 5.5 VDD 5.5 5.5 VDD 0.2 VDD 0.3 VDD 3.5 V MHz k pF s s s s s s s s V Unit V
No. 4907-3/21
LC75710NE, 75711NE, 75712E Electrical Characteristics within the Allowable Operating Ranges
Parameter Input high level current Input low level current Symbol IIH IIL VOH1 Output high level voltage VOH2 VOH3 VOH4 Output low level voltage Output off voltage Pull-down resistors Oscillator frequency Hysteresis voltage Supply current VOL VOFF R1 R2 fOSC VH IDD Conditions DI, CL, CE, RES, OSCI: Vi = 5.5 V DI, CL, CE, RES, OSCI: Vi = 0 V AM1 to AM35: IO = 1 mA AA1 to AA3: IO = 10 mA AA4 to AA8, G1 to G16: IO = 20 mA OSCO: IO = 0.5 mA OSCO: IO = -0.5 mA AM1 to AM35, AA1 to AA8, G1 to G16: VFL = VDD - 50 V AM1 to AM35: VDD - VFL = 48 V AA1 to AA8, G1 to G16: VDD - VFL = 48 V R = 10 k, C = 30 pF DI, CL, CE Outputs open, fOSC = 2.7 MHz, VFL = VDD - 50 V 140 70 2.16 0.5 5 2.7 -5 VDD - 1.0 VDD - 1.0 VDD - 2.0 VDD - 2.0 0 VDD 2.0 VDD - 49 650 325 3.24 V V k MHz V mA V min typ max 5 Unit A A
Note: Since this IC incorporates high voltage ports it is easily damaged by static discharges. Therefore, extra care is required when handling this IC.
Block Diagram
No. 4907-4/21
LC75710NE, 75711NE, 75712E Pin Functions
Pin VDD VSS VFL DI CL CE No. 1 1 1 1 1 1 Pin circuit Function Logic block power supply: +5 V (typical) Logic block power supply: ground Driver block power supply Serial data interface DI: Transfer data CL: Synchronization clock CE: Chip enable
OSCI OSCO
1 1
External oscillator RC circuit connections
RES
1
System reset input
AM1 to AM35 AA1 to AA3
38
Anode outputs Pull-down resistors are built in.
AA4/G16 AA5/G15 AA6/G14 AA7/G13 AA8/G12
5
Anode/grid outputs These pins function as grid output pins when the number of displayed digits is selected to be between 12 and 16 digits with the "Grid register load" instruction. Pull-down resistors are built in.
G1 to G11
11
Grid outputs Pull-down resistors are built in.
TEST
1
LSI testing This pin must be connected to VSS during normal operation.
No. 4907-5/21
LC75710NE, 75711NE, 75712E Block Functions 1. AC (address counter) AC is a counter that provides addresses for DCRAM and ADRAM. The address is modified automatically by internal operations to maintain the VFD display state. 2. DCRAM (data control RAM) DCRAM is RAM that holds the display data, which is expressed as 8-bit character codes. (These character codes are converted to 5 x 7 dot matrix patterns using the CGROM and CGRAM memories.) DCRAM has a capacity of 64 x 8 bits, and can hold the data for 64 characters. The relationship between the 6-bit DCRAM address in AC and the display position on the VFD display is described below. * When the DCRAM address in AC is 00H. (16 digits displayed)
Display digit DCRAM address (hexadecimal) 16 0F 15 0E 14 0D 13 0C 12 0B 11 0A 10 09 9 08 8 07 7 06 6 05 5 04 4 03 3 02 2 01 1 00
However, the DCRAM address moves as follows when a display shift is performed by specifying MDATA.
Display digit DCRAM address (hexadecimal) 16 10 15 0F 14 0E 13 0D 12 0C 11 0B 10 0A 9 09 8 08 7 07 6 06 5 05 4 04 3 03 2 02 1 01 Right shift
Display digit DCRAM address (hexadecimal)
16 0E
15 0D
14 0C
13 0B
12 0A
11 09
10 08
9 07
8 06
7 05
6 04
5 03
4 02
3 01
2 00
1 3F
Left shift
Note: The 6-bit DCRAM addresses are expressed in hexadecimal.
3. ADRAM (additional data RAM) ADRAM is RAM used to store ADATA display data. ADRAM has a 16 x 8-bit capacity and the stored display data is output directly without using CGROM and CGRAM. The relationship between the 4-bit ADRAM address in AC and the display position on the VFD display is described below. * When the ACRAM address in AC is 0H. (16 digits displayed)
Display digit ADRAM address (hexadecimal) 16 F 15 E 14 D 13 C 12 B 11 A 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0
However, the ADRAM address moves as follows when a display shift is performed by specifying ADATA.
Display digit ADRAM address (hexadecimal) 16 0 15 F 14 E 13 D 12 C 11 B 10 A 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 Right shift
Display digit ADRAM address (hexadecimal)
16 E
15 D
14 C
13 B
12 A
11 9
10 8
9 7
8 6
7 5
6 4
5 3
4 2
3 1
2 0
1 F
Left shift
Note: DCRAM and ADRAM addresses are expressed in hexadecimal. MSB DCRAM address DA5 DA4 DA3 DA2 DA1 LSB DA0
Hexadecimal MSB ADRAM address RA3 RA2 RA1
Hexadecimal LSB RA0
Hexadecimal
Example: When the DCRAM address is 3EH. DA5 1 DA4 1 DA3 1 DA2 1 DA1 1 DA0 0
No. 4907-6/21
LC75710NE, 75711NE, 75712E 4. CGROM (character generator ROM) CGROM is ROM that is used to generate the 160 different 5 x 7 dot matrix character patterns. It has a capacity of 160 x 35 bits. When 8-bit character codes are written to DCRAM, the CGROM character pattern corresponding to this 8-bit character code is displayed at the VFD display position corresponding to the DCRAM address in AC. Tables 3 to 5 show the correspondence between the character codes and the character patterns. 5. CGRAM (character generator RAM) CGRAM is RAM to which user programs can write arbitrary data. Up to eight 5 x 7 dot matrix character patterns can be stored in the CGRAM. CGRAM has a capacity of 8 x 35 bits. To display a character pattern stored in CGRAM, write one of the character codes shown at the left of tables 3 to 5 to DCRAM. The CGRAM character pattern will be displayed at the VFD position corresponding to the DCRAM address in AC. Reset Function The LC75710NE series accepts a reset when a low level is applied to the RES pin. On a reset the LC75710NE series creates a display with all VFD lamps turned off. However, note that the values in DCRAM, ADRAM, and CGRAM, as well as the values of the duty cycle register (intensity) and the grid register (number of digits) are undefined following a reset. Therefore, before turning on display with a display on/off control instruction, these values must be initialized. In particular, the following instructions must be executed when power is first applied. * * * * * * * Display blink DCRAM data write ADRAM data write (if ADRAM is used) CGRAM data write (if CGRAM is used) Set AC address Grid register load Intensity adjustment (dimmer)
Initial state settings
After executing the above instructions the display must be turned on by executing a "Display on/off control" instruction. Note that incorrect display may occur if the number of displayed digits and the intensity are not set up in advance. This can occur in cases where a display on/off control instruction is executed before the grid register load and intensity adjustment instructions are executed. To prevent this problem, always execute the following three instructions together as a single set. * Grid register load * Intensity adjustment (dimmer) * Display on/off control
No. 4907-7/21
LC75710NE, 75711NE, 75712E Data Input 1. Serial control data consists of an 8-bit address and a 24-bit instruction. The address is used as a chip select function when multiple ICs are connected to the same bus. The table shows the address for the LC75710NE series.
Address B0 1 B1 1 B2 1 B3 0 A0 0 A1 1 A2 1 A3 0
Note: Only one instruction, the "CGRAM data write" instruction, consists of 56 bits. See Table 1 for instruction code details.
2. DI, CL, CE signal timing
Data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When the microprocessor sends multiple instructions to the LC75710NE series, it must wait long enough for the LC75710NE series to complete the execution of each instruction before sending the next instruction.
No. 4907-8/21
Table 1 Instruction Table
Code D7 D6 D5 Blinks the display. M = 1: MDATA specification, A = 1: ADATA specification *1 Turns the display on or off. O = 1: Display on, O = 0: Display off * * * * Write data (character code) * Write data*2 * * * * * * * * * * * * * * * * * * * * * Loads a DCRAM and ADRAM address into AC (address counter). Adjusts the VFD intensity according to the duty cycle data. Specifies the DCRAM (data control RAM) address and writes data. Specifies the ADRAM (additional data RAM) address and writes data. Specifies the CGRAM (character generator RAM) address and writes data. * * * * * * * * * * * * * * Shifts the display. R/L = 1: Left shift, R/L = 0: Right shift Sets the number of digits displayed according to the grid number data. 18 s 18 s 18 s 0 s 18 s 0 s 18 s 18 s 18 s D4 D3 D2 D1 D0 Description Execution time (maximum)*3
Instruction Grid Grid * * * * * ADATA * CGRAM address * * DCRAM address Duty cycle data * DCRAM address * * * * * * * * * * * * * *
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
Display blink A A R/L O
1
0
1
M
A
Blink cycle data
Display on/off control
0
0
0
1
*
M
Display shift
0
0
1
0
*
M
Grid register load
0
0
1
1
Grid number data
Set AC address * *
0
1
0
0
ADRAM address
Intensity adjustment (dimmer)
0
1
0
1
*
*
DCRAM data write
0
1
1
0
*
*
ADRAM data write *
0
1
1
1
ADRAM address
CGRAM data write
1
0
0
0
*
*
LC75710NE, 75711NE, 75712E
*: Don't care. Note: 1.
2. The table below shows the structure of the CGRAM data write instruction. Code D46 D45 D44 D43 D42 D41 D40 D39 D38 * * D37 D36 D35 D34 * * * Write data D0 CGRAM address
D55 D54 D53
D52
D51 D50
D49 D48 D47
1
0
0
0
*
*
*
*
No. 4907-9/21
3. fOSC = 2.7 MHz
LC75710NE, 75711NE, 75712E Detailed Instruction Descriptions 1. Display blink........................................
Code D23 D22 1 0 D21 1 D20 D19 M A D18 D17 D16 D15 BC2 BC1 BC0 G16 D14 D13 D12 D11 D10 D9 D8 G9 D7 G8 D6 G7 D5 G6 D4 G5 D3 G4 D2 G3 D1 G2 D0 G1 G15 G14 G13 G12 G11 G10
M, A: Data that specifies the blinking operation
M 0 0 1 1 A 0 1 0 1 Display operating state Neither MDATA nor ADATA blinks. Only ADATA blinks. Only MDATA blinks. Both ADATA and MDATA blink.
BC0 to BC2: Blink period setting
BC2 BC1 BC0 HEX 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 Blink Period (s)*1 (when fOSC is 2.7 MHz) Blink operation is stopped. 0.1 0.2 0.3 0.4 0.5 0.8 1.0
G1 to G16: Blinking digit specification Each bit Gn (where n is an integer between 1 and 16) specifies that blinking be applied to grid output pin Gn when the corresponding bit Gn is 1. This instruction is used to specify the blinking operation. Not only can an arbitrary digit be specified, but MDATA and ADATA can also be specified. There are also seven blinking periods. Note: 1. When the blinking period needs to be controlled precisely the display should be blinked by repeatedly turning the display on and off using the display on/off control instruction. 2. Display on/off control ..........................
Code D23 D22 0 0 D21 0 D20 D19 1 * D18 D17 D16 D15 M A O G16 D14 D13 D12 D11 D10 D9 D8 G9 D7 G8 D6 G7 D5 G6 D4 G5 D3 G4 D2 G3 D1 G2 D0 G1 G15 G14 G13 G12 G11 G10
*: Don't care.
M, A: Specifies the data to be turned on or off.
M 0 0 1 1 A 0 1 0 1 Display operating state Both MDATA and ADATA turn off. Only ADATA turns on. Only MDATA turns on. Both ADATA and MDATA turn on.
O: On/off control
O 0 1 Off On Display state
When the display is turned off with an O value of 0, the data can be displayed immediately with an O value of 1 since the display data remains in DCRAM.
No. 4907-10/21
LC75710NE, 75711NE, 75712E G1 to G16: Display digit specification Each bit Gn (where n is an integer between 1 and 16) specifies that the corresponding grid output pin Gn be turned on when that bit (Gn) is 1. This instruction is used to specify the display on/off control operation. Not only can an arbitrary digit be specified, but MDATA and ADATA can also be specified. 3. Display shift .........................................
Code D23 D22 0 0 D21 1 D20 D19 0 * D18 D17 D16 D15 M A R/L * D14 D13 * * D12 D11 D10 * * * D9 * D8 * D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 *
*: Don't care.
M, A: Specifies the data to be shifted.
M 0 0 1 1 A 0 1 0 1 Shift operating state Neither MDATA nor ADATA are shifted. Only ADATA is shifted. Only MDATA is shifted. Both MDATA and ADATA are shifted.
R/L: Shift direction specification
R/L 0 1 Right shift Left shift Shift direction
4. Grid register load .................................
Code D23 D22 0 0 D21 1 D20 D19 1 D18 D17 D16 D15 * D14 D13 * * D12 D11 D10 * * * D9 * D8 * D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 * GN3 GN2 GN1 GN0
*: Don't care.
GN0 to GN3: Displayed digits specification
GN3 GN2 GN1 GN0 HEX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 A B C D E F G1 to G16 G1 G1 to G2 G1 to G3 G1 to G4 G1 to G5 G1 to G6 G1 to G7 G1 to G8 G1 to G9 G1 to G10 G1 to G11 G1 to G12 G1 to G13 G1 to G14 G1 to G15 Digits Controlled
The AA4/G16, AA5/G15, AA6/G14, AA7/G13, and AA8/G12 anode/grid output pins function as grid output pins if between 12 and 16 digits are selected. Also, this instruction must be executed prior to turn the display on since the value of the grid register is undefined immediately after power is applied.
No. 4907-11/21
LC75710NE, 75711NE, 75712E 5. Set AC address.....................................
Code D23 D22 0 1 D21 0 D20 D19 0 D18 D17 D16 D15 * D14 D13 * D12 D11 D10 D9 D8 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 * RA3 RA2 RA1 RA0 DA5 DA4 DA3 DA2 DA1 DA0
*: Don't care.
DA0 to DA5: DCRAM address DA0....................LSB (least significant bit) DA5....................MSB (most significant bit) RA0 to RA3: ADRAM address RA0 ....................LSB RA3 ....................MSB This instruction loads the 6-bit DA0 to DA5 DCRAM address and the 4-bit RA0 to RA3 ADRAM address into AC. 6. Intensity adjustment .............................
Code D23 D22 0 1 D21 0 D20 D19 1 * D18 D17 D16 D15 * * * DC7 D14 D13 D12 D11 D10 D9 D8 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 * DC6 DC5 DC4 DC3 DC2 DC1 DC0
*: Don't care.
DC0 to DC7: Duty cycle data (intensity adjustment data) DC0 ....................LSB DC7 ....................MSB The data in the 8 bits DC0 to DC7 sets the VFD intensity to one of 240 levels. Since the value in the duty cycle register is undefined immediately after power is applied, the display intensity is not determined at that point. Therefore, applications must execute this instruction before turning on the display. Applications can adjust the intensity using the duty cycle register and grid register. The duty cycle register value sets the pulse width (A) and the grid register value sets the period (B). See Figure 3 for the grid timing chart details.
No. 4907-12/21
LC75710NE, 75711NE, 75712E 7. DCRAM data write ..............................
Code D23 D22 0 1 D21 1 D20 D19 0 * D18 D17 D16 D15 * * * * D14 D13 * D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DA5 DA4 DA3 DA2 DA1 DA0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
*: Don't care.
DA0 to DA5: DCRAM address DA0....................LSB DA5....................MSB AC0 to AC7: DCRAM write data (character code) AC0 ....................LSB AC7 ....................MSB This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code (see Tables 3 to 5) and is converted to 5 x 7 dot matrix display data using CGROM and CGRAM.
8. ADRAM data write..............................
Code D23 D22 0 1 D21 1 D20 D19 1 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 * RA3 RA2 RA1 RA0 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1
*: Don't care.
RA0 to RA3: ADRAM address RA0 ....................LSB RA3 ....................MSB AD1 to AD8: ADATA display data There are 8 bits of additional display data, referred to as ADATA, in addition to the 5 x 7 dot matrix of display data (MDATA). This data is used to generate arbitrary dot patterns without using CGROM or CGRAM. The figures show the correspondence between these data types. In particular, when ADn = 1 (where n is an integer between 1 and 8), the dot AAn will be turned on.
ADATA AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AA1 AA2 AA3 AA4/G16 AA5/G15 AA6/G14 AA7/G13 AA8/G12
Corresponding output pin
No. 4907-13/21
LC75710NE, 75711NE, 75712E 9. CGRAM data write ..............................
Code D55 D54 1 0 D53 0 D52 D51 0 * D50 D49 D48 D47 * * * CA7 D46 D45 D44 D43 D42 D41 D40 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Code D39 D38 * * D37 * D36 D35 * * D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 CD35 CD34 CD33 CD32 CD31 CD30 CD29 CD28 CD27 CD26 CD25
Code D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 CD24 CD23 CD22 CD21 CD20 CD19 CD18 CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9
Code D7 D6 D5 CD6 D4 D3 D2 D1 D0 CD8 CD7 *: Don't care. CD5 CD4 CD3 CD2 CD1
CA0 to CA7: CGRAM address CA0 ....................LSB CA7 ....................MSB CD1 to CD35: CGRAM write data (5 x 7 dot matrix display data) The bit CDn (where n is an integer between 1 and 35), corresponds to the AMn dot display data. The figure below shows the positional relationship for this display data.
No. 4907-14/21
LC75710NE, 75711NE, 75712E Usage Notes 1. Power supply sequence The sequences shown below must be followed when turning the power supply on and off. (See Figure 1.) Power on: Logic block power supply (VDD) on Driver block power supply (VFL) on Display on (by the execution of a display on/off control instruction) Power off: Display off (by the execution of a display on/off control instruction) Driver block power supply (VFL) off Logic block power supply (VDD) off
Fig. 1 Power Supply Sequence 2. Anode output pins The anode output pins AM1 to AM35 are used as the anode outputs that form the 5 x 7 dot matrix due to output current considerations. We recommend using the anode output pins AA1 to AA8 for other anode output functions. If the anode waveform is distorted and the VFD glows slightly (smearing) due to the VFD panel used or wiring considerations, try using a lower oscillator frequency. Refer to Figure 2 when determining the oscillator frequency.
Fig. 2 Oscillator Frequency
No. 4907-15/21
LC75710NE, 75711NE, 75712E
Fig. 3 Grid Timing Chart (16 display digits)
No. 4907-16/21
LC75710NE, 75711NE, 75712E Table 2 Instruction/Display Correspondence (LC75710NE)
No. 1 Instruction (hexadecimal) Power application (Initialization with the RES pin) DCRAM data write 6 * 0 0 2 0 Display Initializes the IC. The display will be in the off state. Writes display data " " to DCRAM address 00H. Operation
2
3
DCRAM data write 6 * 0 1 4 F
Writes display data "O" to DCRAM address 01H.
4
DCRAM data write 6 * 0 2 5 9
Writes display data "Y" to DCRAM address 02H.
5
DCRAM data write 6 * 0 3 4 E
Writes display data "N" to DCRAM address 03H.
6
DCRAM data write 6 * 0 4 4 1
Writes display data "A" to DCRAM address 04H.
7
DCRAM data write 6 * 0 5 5 3
Writes display data "S" to DCRAM address 05H.
8
DCRAM data write 6 * 0 6 2 0
Writes display data " " to DCRAM address 06H.
9
DCRAM data write 6 * 0 7 2 0
Writes display data " " to DCRAM address 07H.
10
DCRAM data write 6 * 3 D 4 9
Writes display data "I' to DCRAM address 3DH.
11
DCRAM data write 6 * 3 E 5 3
Writes display data "S" to DCRAM address 3EH.
12
DCRAM data write 6 * 3 F 4 C
Writes display data "L" to DCRAM address 3FH.
13
Grid register load 3 8 * * * *
Specifies that the display has 8 digits.
14
Intensity adjustment 5 * F F * * SANYO
Sets the VFD intensity to the maximum.
15
Display on/off control 1 5 0 0 F F
Turns on the VFD for only the digits G1 to G8 in MDATA.
16
Display shift 2 5 * * * *
SANYO
L
Shifts the display (MDATA only) to the left.
17
Display shift 2 5 * * * *
SANYO
LS
Shifts the display (MDATA only) to the left.
18
Display shift 2 5 * * * *
ANYO
LSI
Shifts the display (MDATA only) to the left.
19
Set AC address 4 * 0 0 * *
SANYO
Returns the display to the original state.
* Don't care. Note: The example above assumes the use of an 8 digit 5 x 7 dot matrix VFD, and CGRAM and ADRAM are not used.
No. 4907-17/21
LC75710NE, 75711NE, 75712E Table 3 LC75710NE CGROM (Version for use in USA and Japan)
Note: The character pattern (output data) is undefined if the character codes 00001000B to 00011111B, 10000000B to 10011111B, or 11100000B to 11111111B are written to DCRAM.
No. 4907-18/21
LC75710NE, 75711NE, 75712E Table 4 LC75711NE CGROM (Version for use in Europe)
Note: The character pattern (output data) is undefined if the character codes 00001000B to 00011111B or 11000000B to 11111111B are written to DCRAM.
No. 4907-19/21
LC75710NE, 75711NE, 75712E Table 5 LC75712E CGROM (Version for use in Europe)
Note: 1. The character pattern (output data) is undefined if the character codes 00001000B to 00011111B or 11000000B to 11111111B are written to DCRAM. 2. Both the LC75711NE and the LC75712E are for use in the European market. These products differ in that the LC75712E CGROM takes handling a 5 x 8 dot matrix into consideration. In particular, this product allows the AA1 to AA5 anode output pins to be used to form a 5 x 8 dot matrix artificially, with the combination of AM1 to AM35 and AA1 to AA5. Adopting this structure allows applications to provide improved display quality for European characters, especially those requiring an umlaut.
No. 4907-20/21
LC75710NE, 75711NE, 75712E
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any and all SANYO products described or contained herein fall under strategic products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of Japan, such products must not be exported without obtaining export license from the Ministry of International Trade and Industry in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 1998. Specifications and information herein are subject to change without notice. No. 4907-21/21

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